Computer Hardware Architecture
Syllabus

Be able-tudes
CS 262 / Eng 262

 

Exam I

Exam II

 

Exam I

  1. Be able to identify various major sections of Medusa from the block diagram with labels removed.  Identify the data path, the microsequencer, and the external world.  Also be able to distinguish between Medusa's use of ROM, RAM, and storage registers.  Which, ROM or RAM, is used as microstore in the sequencer?  Which is used in main memory?  Why must we have some RAM memory in our computer?  Be able to explain how Medusa shuffles data within the data path in loading a word into the accumulator and preparing for the next OPCODE.  And explain how sequencer "words" implement each step of data path information transfer.
  2. Be able to identify the scratch pad memory, ALU, main memory, I/O port, and other subsystems on a blank drawing of Medusa's layout.  Be able to show the direction of information flow in the busses.
  3. Be able to explain the difference between RAM and ROM as well as the difference between SRAM and DRAM.  What do we use in Medusa, and why?
  4. Be able to identify multiplexers and decoders and describe their roles, e.g. in the sequencer or within microstore in the sequencer.
  5. Be able to identify the sources of the addresses used to jump within the microprogram in the sequencer.
  6. Be able to explain the need for a debounce circuit and how one works.
  7. Be able to give the truth table for a NAND or NOR gate and explain how TTL logic responds to logic-1, logic-0, and open circuit inputs.  Also be able to describe the stability of logic circuits in terms of the ranges of acceptable voltages for logic-0 and for logic-1.
  8. Be able to identify the pin numbers on chips from their physical appearance.  Also be able to explain chip handling procedures to reduce chip damage from static electricity.  Also explain logic contention when two chips' outputs are connected to the same electrical terminal (connection).
  9. Be able to sketch a 2x4 decoder made of NAND gates and adapt it to make a multiplexer and/or a demultiplexer.  Be able to explain the purpose of each.
  10. Be able to distinguish between "combinational" and "sequential" logic.
  11. Be able to sketch the electronic (transistors, resistors, etc.) diagram for a three-input NAND or three-input NOR gate.
  12. Be able to sketch the logic diagram for a simple SR latch made of NAND gates.  Be able to explain why it is called a latch.  Be able to write the truth table for Q(t+1) as a function of S, R, and Q(t) for all possible combinations and explain why some states are ambiguous.
  13. Be able to sketch the logic diagram for a 4 to 1 multiplexer (or a 1 to 4 demultiplexer) made of NAND gates.  Explain the purpose of each.
  14. Be able to sketch a clocked SR latch and reproduce its S, R, and Q(t) truth table.  Explain why a clock input is important when latches are being used in static RAM.
  15. Be able to sketch a master-slave flipflop and explain how it functions.  Why is the clock input inverted for the slave and what timing considerations are important in the information transfer to the slave?  Also be able to explain why the master-slave latch is useful in eliminating electrical errors/problems.
  16. Be able to sketch the master-slave JK flipflop with Set and Clear inputs and explain the type of control that is provided by all of its logic inputs JK, Set, and Clear.  Also sketch and explain the JK-ff truth table.  Particularly be able to explain why there is no ambiguous state for this flipflop.
  17. Be able to assemble JK-ff's into shift registers and counters (both synchronous and ripple types).
  18. Be able to sketch the steering logic for parallel input to a 4-bit shift register and explain how its bit pattern can sent serially.  Be able to explain why this parallel to serial and its converse (serial-to-parallel) are important in computer communication.
  19. Be able to construct truth tables for the above devices.
  20. Be able to identify the number of unique addresses (or codes) available in a given number of bits.  For example: How many unique patterns are possible with a 4-bit word?  An 8-bit word?  A 10-bit word?  A 16-bit word?
  21. Be able to convert binary numbers to decimal numbers and vice versa, and to perform binary addition.
  22. Be able to describe and explain the six levels of computer architecture (Tanenbaum).  What is meant by a virtual machine?  What is meant by the statement that "hardware and software are logically equivalent"?
  23. Be able to describe and explain the advances and new concepts that distinguish the five generations of computers.
  24. What characterizes a Von Neumann machine?  Is Medusa a Von Neumann machine?  Be able to justify your answer.
  25. Be able to describe and decode the color coding scheme of resistors.  For example, what are the values of these two resistors?

    0 = BlacK
    1 = BrowN
    2 = Red
    3 = Orange
    4 = Yellow
    5 = GreeN
    6 = BluE
    7 = Violet
    8 = GraY
    9 = White
  26. Explain the terms voltage and current in electronic usage.  Which determines the logic level in our computer?
  27. Be able to solve problems involving Ohm's Law and power calculations.  Be able to define and explain the basic units of electric circuits (electrons, coulombs, volts, ohms, etc.).  Differentiate between signal propagation speed and electron drift speed in circuits.
  28. Be able to describe the role of basic electronic components (e.g. capacitor, resistor, etc.) in electronic circuits.
  29. Be able to explain the effect of parallel and series connections of capacitors and resistors.
  30. What is the meaning and the purpose of tri-stated outputs within a computer?  When a bus wire becomes disconnected from a chip what is the equivalent logic: 0, 1, or tri-state?  Can you guarantee that all chips will interpret it that way?  Explain your answer.
  31. Explain why there must be at least two wires interconnecting electronic components.  In other words why do we call them electrical circuits?
  32. Be able to sketch and explain how an electron beam is swept across an oscilloscope from left to right. Include graphs of the deflection voltage signals.
  33. What does the oscilloscope measure?  How is the information displayed?  Identify the principal subsystems of the oscilloscope and explain the operation and purpose of each.  Explain how to read an oscilloscope display screen
  34. What is the purpose of the trigger control on an oscilloscope?  Why is it needed?

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Syllabus
Computer Hardware Architecture

Exam II

  1. Be able to explain how the oscilloscope display operates --what goes on inside the cathode ray tube to produce the bright lines observed.  What are the similarities and the differences in the oscilloscope display and the monitor display of a computer terminal?  What is the purpose of the trigger control on an oscilloscope and why is it needed?  Be able to read communications data as displayed on the oscilloscope.
  2. Be able to describe the general purpose of the UART.
  3. Be able to explain the method employed by the UART to keep the transmitter of the sender and the receiver in synchronism and explain how a failure is detected.
  4. Be able to describe what kind of protocol information must be communicated between sender and receiver for communication between UARTs at two stations.  How is this protocol information set within the UART?  What protocol information is set external to the UART?
  5. Be able to outline the timing requirements in communicating between a UART and its local processor.  Identify the pins used in this timing with the pinout diagram in the manual appendix.
  6. Be able to explain the four-phase clock timing diagram (Figure 6.5).
  7. Be able to outline why the UART oscillator runs at 16xBAUD rate rather than the BAUD frequency.
  8. Given the UART chip pinout, be able to identify which pins are input and which are output pins.  Also explain the timing used on each pin to make the UART data echo to the monitor screen while storing the same byte in RAM.
  9. Be able to explain tri-stating, and the reason that the UART must have tri-stated outputs for both its status word and its received word output.
  10. Explain the use of both the START bit and the STOP bit in the synchronization of bit sampling within the received signal.
  11. Be able to describe both physical and logical schemes for reducing information corruption by line noise.
  12. Be able to explain the error checking used in the UART chip - parity error, framing error, and overrun error.  What is the likely cause of these errors in serial communications?  How does the computer "know" that one or more of these errors has occurred?
  13. Be able to explain the Hamming error detection and correction method, and to solve problems involving Hamming codes. 
  14. Be able to demonstrate how an Exclusive-OR gate can be used as a parity checker for input data and as a parity setter for output words in either an even or an odd parity protocol.
  15. Be able to set up and analyze a NAND implemented logic circuit for Boolean analysis to discover if it carries out a desired logic function -- be particularly familiar with NAND implementation of standard logic circuits AND, OR, NOR, EXOR operations.  These will likely employ Boolean absorption theorems and the DeMorgan theorem in transforming logic expressions.
  16. Be able to sketch a binary number system that has both positive and negative numbers and explain the 2's complement number system.  In particular show how to obtain sums and differences in 2's complement arithmetic.
  17. Be able to identify ASCII codes for letters and numbers including start and stop bits.  (You need NOT memorize the ASCII table.)
  18. Given a 4-bit adder, and the need to check its output for ZERO, NEGATIVE, NON-ZERO-POSITIVE, or OVERFLOW, be able to design logic circuits that give logic-1 flags for each of these conditions.  (You have all the standard logic gates at your disposal.)
  19. Be able to check, set, and clear bit flags in an eight bit status register using AND masks with bit-wise AND or OR operations.
  20. Be able to set up the logic section of a bit-slice ALU including its decoder.  Possible operations can be: A-only, NOT-A, A AND B, A OR B and Zero.
  21. Be able to explain the bit slice concept of parallel processed data -- in particular for the laboratory ALU.  This includes doing longhand calculation of 2's-complement addition and subtraction showing the need for carry-in and carry-out signals.
  22. Be able to explain the use of the EXOR gate for both half and full adders and devise a carry-out logic circuit.
  23. Be able to explain how the EXOR gate can be deployed as an electronically-selected invertor.
  24. Be able to describe SRAM and DRAM and significant advantages and disadvantages of each.

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Syllabus
Computer Hardware Architecture

Page last updated 1/24/2000 by S. Shedd